1. Field of the Invention
The present invention relates generally to methods for revising patterned conductor layer layouts employed for fabricating microelectronic fabrications. More particularly, the present invention relates to methods for efficiently revising patterned conductor layer layouts employed for fabricating microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
Integral to the fabrication of patterned microelectronic conductor layers within microelectronic fabrications is the design and development of patterned microelectronic conductor layer layouts employed for fabricating patterned microelectronic conductor layers within microelectronic fabrications. Such patterned microelectronic conductor layer layouts are generally designed and developed employing computer assisted design software programs and computer assisted simulation software programs, such as to verify prior to production of a particular microelectronic fabrication having fabricated therein a particular patterned microelectronic conductor layer layout the operational properties of the microelectronic fabrication, such as not to wastefully expend manufacturing resources when fabricating the particular microelectronic fabrication.
In the process of designing and developing patterned microelectronic conductor layer layouts for use when fabricating microelectronic fabrications, it is common in the art of microelectronic fabrication to employ any of several iterative methods for purposes of optimizing a patterned microelectronic conductor layer layout such as to in turn provide an enhanced microelectronic fabrication performance. While such iterative methods do in fact provide an optimized patterned microelectronic conductor layer layout which in turn provides an enhanced microelectronic fabrication performance, such iterative methods are often time consuming, in particular when employed for optimizing a library of patterned microelectronic conductor layer layouts which is employed within a corresponding library of related microelectronic fabrications such as to in turn optimize performance of the corresponding library of related microelectronic fabrications.
It is thus desirable in the art of microelectronic fabrication to provide methods for efficiently designing patterned microelectronic conductor layer layouts for use when fabricating microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
Various methods, apparatus and systems have been disclosed in the microelectronic fabrication art to assist in efficiently designing microelectronic layer layouts and microelectronic structure layouts which are employed when fabricating microelectronic fabrications.
Included among the methods, apparatus and systems, but not limited among the methods, apparatus and systems are methods, apparatus and systems disclosed within: (1) Yoshimura, in U.S. Pat. No. 5,446,675 (a method, apparatus and system for using hierarchally organized data to design a semiconductor integrated circuit microelectronic fabrication layout, wherein a plurality of macros and circuit logic cells within the semiconductor integrated circuit microelectronic fabrication layout is cross-referenced employing two types of pointers); (2) Scepanovic et al., in U.S. Pat. No. 6,134,702 (a method and system for designing a semiconductor integrated circuit microelectronic fabrication layout which employs an iterative assignment of flexibly placeable cells in subsets of increasingly smaller number, in conjunction with a corresponding iterative determination of various circuit performance penalties for placing the subsets within particular configurations); and (3) Takahashi, in U.S. Pat. No. 6,154,873 (a method, apparatus and system for hierarchal design of semiconductor integrated circuit microelectronic fabrication layouts wherein hard macro blocks are first positioned and interconnected with patterned conductor layers which cross over soft macro blocks, and wherein a circuit performance penalty is evaluated with respect to the soft macro blocks such as to provide for optimal placement of cell components within columns or rows within the soft macro blocks).
Desirable in the microelectronic fabrication art are additional methods, apparatus and systems which may be employed for efficiently designing patterned microelectronic conductor layer layouts for use when fabricating microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.